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Lead SoC Architect

EnCharge AI

EnCharge AI

IT
Santa Clara, CA, USA
Posted on Friday, July 21, 2023

The SoC Architect will lead the architectural definition and development, including hardware and software, of the I/O subsystem for EnCharge AI's leading edge AI inference SoC. The I/O subsystem is expected to include PCIe interfaces with SR-IOV support for virtualization, DMA engines for high-speed data transfer between the host and the card, a memory subsystem consisting of multiple memory controllers and a RISC-V based multi-core CPU subsystem, in addition to standard interfaces for debug and testability such as I2C and JTAG. The RISC-V subsystem is used to orchestrate application execution on the AI compute subsystem in a virtualized environment, as well as data transfer in and out of the SoC.

The candidate is expected to drive the architecture and definition of the low-level hardware/software stack for the PCIe card. This includes comprehensive software definition, based on the expected useage modes of the firmware and device drivers, as well as hardware definition, to drive the architecture of the hardware engines, their interconnection and the overall execution of jobs and data transfer to/from the SoC. Experience with defining boot-up sequences, DFT and reset strategies, debug interfaces and silicon bring-up is also required.

The candidate will also be responsible for driving logic development, integration of custom and third-party IP, developing a verification plan, and liaising with IP vendors.

Role/Responsibilities:

  • Define and develop the spec, architecture, and micro-architecture of PCIe Gen 4/5, LPDDR 4/5, and RISC-V sub-system
  • Lead the development and integration of the various IP
  • Lead bring-up and testing of PCIe and memory sub-system in block and full-chip test environment
  • Manage relationship with IP vendors to procure controllers, PHYs, and other IP
  • Work closely with the architecture and software firmware team for device driver development and use it to drive the microarchitecture of the I/O subsystem
  • Work closely with the PD team to ensure timing closure and PPA goals are met

Qualifications/Required Skills:

  • BS/MS/Ph.D. in EE or CS with 10+ years of experience in chip design
  • Experience with tape out of large-scale SoCs
  • Must have experience in PCIe Gen 4/5, SR-IOV, FLR and familiarity with PCIe driver development
  • Must have experience with LPDDR 4/5 (and optionally HBM)
  • Must have experience with a processor based SoC development
  • Must have experience with chip bring-up
  • Must have knowledge of System Verilog and UVM based verification methodology desired
  • Knowledge of post silicon debug desired
  • Knowledge of design emulation desired